Background:
The 80386 processor was the progenitor of the entire IA32 (32-bit Intel Architecture) processor product line. As time has progressed, Intel has added new hardware and software features to the IA32 processor family with each new generation. Starting with the Pentium Pro processor, all Intel IA32 processors (including Celerons and Xeons) up to and including the Pentium III processor were based on the P6 processor core. The Pentium 4 processor was based on the NetBurst core architecture, while the Pentium M, Core Solo and Core Duo processors are variants on the Pentium III processor core. In mid-2006, Intel introduced processors based on the new Core 2 Microarchitecture, an enhanced version of the Pentium M processor core. To date, all processors introduced since the Pentium Pro use a variation on the Front Side Bus (FSB) protocol introduced in the Pentium Pro processor. The processor is interfaced to the remainder of the system board components via the chipset. Like Intel’s processors, the chipset’s role has also evolved over time.
Course Length: 4 days
Who Should Attend?
This course is intended for both software and hardware designers involved in validation, test and debug or performance evaluation. In addition, it provides valuable background for engineering marketing and support personnel.
Course Contents:
In conjunction with the accompanying book, The Unabridged Pentium 4 (published by Addison-Wesley Longman) and a detailed PowerPoint presentation, MindShare's Core Processor Architecture course provides a detailed discussion of the Core processor hardware and software features.
- Overview of the Processor’s Role
- Overview of the Processor Internal Architecture
- Overview of the System Architecture
- Front Side Bus
- Toggle Mode Transfer Order
- FSB Electrical Characteristics
- Intro to the FSB
- CPU Arbitration
- Priority Agent Arbitration
- Request Phase
- Snoop Phase
- Response and Data Phases
- Deferred Transactions
- Interrupt Delivery
- Introduction to Some Core Concepts
- The P6 Core Overview
- Pentium M
- Core Solo/Duo
- Core 2 Duo
- The Celerons and Xeons
- Processor PowerOn Configuration
- Processor Startup
- The Memory Types
- Overview of the L1 Data and L2/L3 Caches
- Overview of SMM
- CPU ID
- Register Set Introduction
- Control Registers
- Eflags Register
- GPRs
- Segmentation in Real Mode
- Segmentation in Protected Mode
- Flat Model
- Paging
- Task Switching
- VM86 Mode
- Virtualization Overview
- IA32e Overview
- Debug Registers
- x87 FPU
- Exceptions
- Machine Check Architecture
- Instruction Set Evolution
- Baseline 386 Instruction Set
- Instructions added by 486
- Instructions added by Pentium
- Instructions added by Pentium Pro
- Instructions added by Pentium II
- Instructions added by Pentium III (SSE)
- Instructions added by Pentium 4 (SSE2)
- Instructions added by Pentium 4 Prescott (SSE3)
Recommended Prerequisites:
None
Corresponding Book:
MindShare’s The Unabridged Pentium 4, IA32 Processor Genealogy textbook (1st Edition).
Author: Tom Shanley
Publisher: Addison Wesley
Additional Courses:
MindShare also offers additional courses based on The Unabridged Pentium 4 book:
IA32 and IA32e Software Architecture - (4-day)
Core APIC Subsystem - (1-day)
Core Front Side Bus - (1-day subset of the Core Processor Architecture class)
Booking Information:
We also customize classes to meet your company's specific needs. For available dates, pricing information or to make a reservation, please contact us