(Embedded) PC technology - a quick overview

Comparison of computerboards form factors

Overview:

A PC motherboard is the main circuit board within a typical desktop computer, laptop or server. It has a number of functions of which the main ones are:

• As a central backbone to which all other modular parts (CPU, RAM, hard drives etc) can be attached as required to create a modern computer
• To accept (on many motherboards) different components (in particular CPU and PCI cards) for the purposes of customization.
• To distribute power to many of the PC components
• To electronically co-ordinate the operation of these, and interface all of these with one another.

As new generations of components have been developed, the standards of motherboards have changed too - for example with AGP being introduced, and more recently PCI Express. However the basic standardized size and layout of motherboard have changed much more slowly, and are controlled by their own standards. This is helped by the fact that in many ways, the list of components a motherboard must include changes far slower than the components themselves. For example, north bridge controllers have changed many times since their original introduction, with many manufacturers bringing out their own versions, but in terms of form factor standards, the requirement to allow for a north bridge has remained fairly static for many years.

Although it is a slower process, form factors do evolve regularly in response to changing demands. The original PC standard (AT) was superseded in 1995 by the current industry standard ATX, which still dictates the size and design of the motherboard in most modern PCs. The latest update to the ATX standard was released in 2004. A divergent standard by chipset manufacturer VIA called EPIA is based upon smaller form factors and its own standards.

Differences between form factors are most apparent in terms of their intended market sector, and involve variations in size, design compromises and typical features. Most modern computers have very similar requirements, so form factor differences tend to be based upon subsets and supersets of these. For example, a desktop computer may require more sockets for maximal flexibility and many optional connectors and other features on-board, whereas a computer to be used in a multimedia system may need to be optimized for heat and size, with additional plug-in cards being less common. The smallest motherboards may sacrifice CPU flexibility in favor of a fixed manufacturer's choice.

 Comparison:

Graphical comparison of phisical sizes:

This image compares the sizes of common form factors to ISO 216 paper sizes (e.g. A4) (Sizes are in mm):

Traditional BIOS versus EFI Framework

The Extensible Firmware Interface (EFI) is a specification that defines a software interface between an operating system and platform firmware. EFI is intended as a significantly improved replacement of the old legacy BIOS firmware interface historically used by all IBM PC compatible personal computers^[1]. The EFI specification was originally developed by Intel, and is now managed by the Unified EFI Forum and is officially known as Unified EFI (UEFI).

History

The original motivation for EFI came during early development of the first Intel-HP Itanium systems in the mid-1990s. PC BIOS limitations (16-bit processor mode, 1 MB addressable space, PC AT hardware dependencies, etc.) were seen as clearly unacceptable for the larger server platforms Itanium was targeting. The initial effort to address these concerns was initially called Intel Boot Initiative and was later renamed to EFI^[2].

EFI specification 1.02 was released by Intel on December 12, 2000. (Version 1.01 was the original issue; it had incorrect legal and trademark information and was quickly withdrawn^[3].)

EFI specification 1.10 was released by Intel on December 1, 2002. It included the EFI driver model as well as several minor enhancements to 1.02.

In 2007, Intel contributed this specification to the UEFI Forum, who is now responsible for its development^[4] and promotion. EFI was renamed to Unified EFI (UEFI) to reflect this; most documentation uses both terms interchangeably.

The UEFI Forum released version 2.1 of the UEFI specification on January 7, 2007; as of March 2007, it is the latest publicly available specification. It added and improved cryptography, network authentication, and the User Interface Architecture (Human Interface Infrastructure in UEFI).

Contents

The interface defined by the EFI specification includes data tables which contain platform information, and boot and runtime services which are available to the OS loader and OS.

Some existing enhancements to PC BIOS, such as the Advanced Configuration and Power Interface (ACPI) and System Management BIOS (SMBIOS), are also present in EFI, as they do not rely on a 16-bit runtime interface.

Services

EFI defines boot services, which include text and graphical console support on various devices, bus, block and file services, and runtime services, such as date, time and NVRAM services.

Device Drivers

In addition to standard architecture-specific device drivers, the EFI specification provides for a processor-independent device driver environment, called EFI Byte Code or EBC. System firmware is required by the UEFI specification to carry an interpreter for any EBC images that resides in or is loaded into the environment. In that sense, EBC is similar to Open Firmware, the hardware-independent firmware used in PowerPC-based Apple Macintosh computers and Sun Microsystems SPARC computers, amongst others.

Some architecture-specific (non-EBC) EFI device driver types can have interfaces for use from the operating system. This allows the OS to rely on EFI for basic graphics and network support until OS specific drivers are loaded.

Boot manager

An EFI boot manager is also used to select and load the operating system, removing the need for a dedicated boot loader mechanism (the OS boot loader is an EFI application).

Disk support

In addition to the standard PC disk partition scheme, Master boot record (MBR), EFI adds support for a GUID Partition Table (GPT), which does not suffer from the same limitations. The EFI specification does not include a description for a file system; implementations of EFI typically support FAT32 as their file system^[5].

The EFI shell

The EFI community has created an open source shell environment^[6].; rather than booting directly into a full OS, on some implementations, the user can boot to the EFI shell. The shell is an EFI application; it can reside directly within the platform ROM, or on a device for which the drivers are in ROM.

The shell can be used to execute other EFI applications, such as setup, OS install, diagnostic or configuration utilities, and system flash updates; it can also be used to play CDs or DVDs without having to boot to a complete operating system, provided that an EFI application with the appropriate features is written. Shell commands also make it possible to copy or move files and directories between supported file systems. Drivers can be loaded and unloaded, and a complete TCP/IP stack can also be used from within the shell.

The EFI shell supports scripting through .nsh files, which are analogous to DOS batch files.

Shell command names are often inherited from the DOS command line interpreter COMMAND.COM or the Unix shell. The shell can be viewed as a functional replacement for the DOS command line interface and the BIOS text user interface.

Extensions

Extensions to EFI can be loaded from virtually any non-volatile storage device attached to the computer. For example, an original equipment manufacturer (OEM) can sell systems with an EFI partition on the hard drive which would add additional functions to the standard EFI firmware stored on the motherboard’s ROM.

Implementation and adoption

Intel Platform Innovation Framework for EFI

The Intel Platform Innovation Framework for EFI (also known as “the Framework”) is a set of specifications developed by Intel in conjunction with EFI. While EFI specifies the OS-to-firmware interface, the Framework specifies the structure used to build the firmware beneath the OS-to-firmware interface.

In particular, the Framework includes all the steps needed to initialize the platform after power-on. These inner workings of firmware are not defined as part of the EFI specification, but some are part of the Platform Initialization Specification developed by UEFI. The Framework has been tested on Intel XScale, Intel Itanium and IA32 platforms.

Compatibility with x86 operating systems that require “legacy BIOS” interfaces to operate is handled through a compatibility support module (CSM). The CSM includes a 16-bit binary (CSM16) supplied by a BIOS vendor and a “thunk” layer to connect CSM16 to the Framework.

Intel developed a reference codebase for the Framework, codenamed “Tiano”. Tiano is a complete, legacy-free firmware implementation that includes support for EFI. Tiano does not include the 16-bit portion of the CSM, but provides the interfaces required to add one supplied by a BIOS vendor. Intel does not make the complete Tiano implementation available to end-users.

A portion of the Tiano codebase (“the Foundation”) has been released as open source to the TianoCore project as the EFI Developer Kit (EDK). This implementation covers EFI and some hardware initialization code, but does not constitute feature-complete firmware by itself. Several licenses have been used for this code, including the BSD license and the Eclipse Public License.

Products based on EFI, UEFI & the Framework specifications are available through independent BIOS vendors, such as American Megatrends (AMI) and Insyde Software. Some vendor implementations are entirely based on the Tiano implementation, while others are designed to be specification compliant without relying on Intel’s reference implementation.^[7]

Platforms that use EFI or the Framework

Intel’s first Itanium workstations and servers, released in 2000, supported EFI 1.02.

Hewlett-Packard’s first Itanium 2 systems, released in 2002, supported EFI 1.10; they were able to boot Windows, Linux, FreeBSD and HP-UX.

All Itanium or Itanium 2 systems that ship with EFI compliant firmware must also comply with all DIG64 specifications.

In November 2003, Gateway introduced the Gateway 610 Media Center, the first x86 Windows-based computer system to use firmware based on the Framework, Insyde Software's InsydeH2O. It still relied on a legacy BIOS implemented as a compatibility support module to boot Windows.

In January 2006, Apple, Inc. shipped their first Intel-based Macintosh computers. These systems use EFI and the Framework instead of Open Firmware, which had been used on their previous PowerPC-based systems.^[8] On April 5, 2006 Apple released Boot Camp which produces a Windows XP Drivers Disk as well as a non-destructive partitioning tool to help users easily install Windows XP. A firmware update was also released which added legacy BIOS support to its EFI implementation. Subsequent Macintosh models shipped with the newer firmware. Now all current Macintosh systems are also able to boot legacy BIOS Operating Systems like Windows XP and Vista.

The grand majority of Intel motherboards ship with Framework-based firmware. During 2005 more than one million Intel systems shipped with the Framework^[9]. New mobile, desktop and server products, using the Framework, started shipping in 2006. For instance, all boards that use the Intel 945 chipset series use the Framework. However, the production firmware usually does not include EFI support, and is limited to legacy BIOS^[10].

Since 2005, EFI has also been implemented on non-PC architectures, such as embedded systems based on XScale cores^[11].

The EDK includes an NT32 target, which allows EFI firmware and EFI applications to run within a Windows application.

In 2007 HP released the 8000 series multifunction printers with EFI compliant firmware.^[12]

Operating systems

• Linux systems have been able to use EFI at boot time since early 2000, using the elilo EFI boot loader. elilo is the only means to boot Linux on IA-64 platforms; it can also be used on IA-32 platforms. As of July 2007, elilo support for x86-64 mode is available through a beta release.

• HP-UX has used EFI as its boot mechanism on IA-64 systems since 2002. OpenVMS has used it on production releases since January 2005.

• Apple has adopted EFI for its line of Intel-based Macs. Mac OS X v10.4 “Tiger” for Intel and Mac OS X v10.5 “Leopard” thoroughly support EFI.

Microsoft Windows

The Itanium versions of Windows 2000 (Advanced Server Limited Edition and Datacenter Server Limited Edition) supported EFI 1.1 in 2002.

Windows Server 2003 for IA64, Windows XP 64-bit Edition, and Windows 2000 Advanced Server Limited Edition, all of which are for the Intel Itanium family of processors, support EFI, a requirement of the platform through the DIG64 specification.^[13]

Microsoft plans to introduce UEFI support for 64-bit x64 with Windows Server 2008. UEFI support for x64 versions of Windows Vista are planned to be included in a service pack,^[14] possibly Vista Service Pack 1.^[15] Microsoft claims that the lack of official support for EFI booting on 32-bit CPUs is due to lack of support from PC manufacturers and vendors. Microsoft’s migration to x64 operating systems is not supportable by EFI 1.10, since the x86-64/EM64T processor extensions required by x64 operating systems were not a supported processor binding. Support for x86-64/EM64T was added in UEFI 2.0.

Microsoft has released a video with Andrew Ritz and Jamie Schwarz explaining Pre-OS support involving UEFI on Vista and Longhorn.^[16]

Intellectual property

According to Ron Minnich, the lead developer for LinuxBIOS, one of the stated goals of EFI is to “protect hardware vendors’ intellectual property”. This raises security concerns and notably makes creating a free software implementation impossible. EFI could be used to create a “DRM BIOS”, thus letting vendors build computers which limit what the user can do.^[17]

x86 - 64

x86-64 is a 64-bit superset of the x86 instruction set architecture. The x86-64 instruction set natively supports Intel's x86 and was designed by Advanced Micro Devices (AMD), who have since renamed it AMD64. This architecture has been cloned by Intel under the name Intel 64 (formerly known as Yamhill, Clackamas Technology, CT, IA-32e, and EM64T).^[1] This leads to the common use of the names x86-64 or x64 as more vendor-neutral terms to collectively refer to the two nearly identical implementations.

x86-64 should not be confused with the Intel Itanium architecture, which is not compatible on the native instruction set level with the x86 or x86-64 architecture.

AMD64

The AMD64 instruction set is currently implemented in AMD's Athlon 64, Athlon 64 FX, Athlon 64 X2,Phenom X4, Phenom X3, Athlon X2, Turion 64, Turion 64 X2, Opteron and later Sempron processors.

History of AMD64

AMD64 was created as an alternative to Intel and Hewlett Packard's radically different IA-64 architecture. Originally announced as "x86-64" in August 2000,^[2] the architecture was positioned by AMD from the beginning as an evolutionary way to add 64-bit computing capabilities to the existing x86 architecture, as opposed to Intel's approach of creating an entirely new 64-bit architecture with IA-64. The AMD64 platform brand and AMD64 logo was created by the 4-person strategic marketing team of Hal Speed, Simon Solotko, Christian Zdebel and Tom King.

The first AMD64-based processor, the Opteron, was released in April 2003.

Architectural features

The primary defining characteristic of AMD64 is its support for 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:

• Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.

• Additional registers: In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased from eight (i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32 to 16. It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent. However, AMD64 still has fewer registers than many common RISC processors (which typically have 32–64 registers) or VLIW-like machines such as the IA-64 (which has 128 registers).

• Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.

• Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (2⁴⁸ bytes). This limit can be raised in future implementations to 16 exbibytes (2⁶⁴ bytes). This is compared to just 4 gibibytes for 32-bit x86. This means that very large files can be operated on by mapping the entire file into the process' address space (which is generally faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.

• Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (2⁴⁰ bytes); the architecture permits extending this to 4 pebibytes (2⁵² bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.

• Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.

• SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision, with the choice of either IEEE 32-bit or 64-bit floating-point mathematics. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they're used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions does not reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.

• No-Execute bit: The “NX” bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors; however, this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4 GiB. AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.

• Removal of older features: A number of "system programming" features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long (64-bit and compatibility) mode. These include segmented addressing (although the FS and GS segments were retained in vestigial form for compatibility with Windows code)^[3], the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in "legacy mode," thus permitting these processors to run 32-bit and 16-bit operating systems without modification.

Virtual Address space details

Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and any chips known to be in the planning stages) do not allow the entire virtual address space of 2⁶⁴ bytes (16 exbibytes, or about 18×10¹⁸ bytes) to be used. Most operating systems and applications will not need such a large address space for the foreseeable future (for example, Windows implementations for AMD64 are only populating 16 tebibytes, or 44 bits' worth), so supporting such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD therefore decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page table lookup). However, bits 48 through 63 of any virtual address must be copies of bit 47 (in a manner akin to sign extension), or the processor will raise an exception. Addresses complying with this rule are referred to as "canonical form." Canonical form addresses run from 0 through 00007FFF`FFFFFFFF, and from FFFF8000`00000000 through FFFFFFFF`FFFFFFFF, for a total of 2⁴⁸ bytes or 256 tebibytes of usable virtual address space.

This "quirk" allows an important feature for later scalability to true 64-bit addressing: many operating systems (including, but not limited to, the Windows NT family) take the higher-addressed half of the address space (named kernel space) for themselves and leave the lower-addressed half (user space) for application code, user mode stacks, heaps, and other data regions. The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000`00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, fixing the contents of the unused address bits prevents their use by operating system as flags, privilege markers, etc., which could become problematic when the architecture is indeed extended to 52, 56, 60 and 64 bits.

The 64-bit addressing mode ("long mode") is a superset of Physical Address Extensions (PAE); because of this, page sizes may be either 4 KiB (2¹² bytes), 2 MiB (2²¹ bytes), or 1 GiB (2³⁰ bytes). However, rather than the three-level page table system used by systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-Directory Pointer Table is extended from 4 entries to 512, and an additional Page-Map Level 4 Table is added, containing 512 entries in 48-bit implementations. In implementations supporting larger virtual addresses, this latter table would either grow to accommodate sufficient entries to describe the entire address range, up to a theoretical maximum of 33,554,432 entries for a 64-bit implementation, or be over ranked by a new mapping level, such as a PML5. Either way, a full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take a bit more than 512 GiB of RAM (about 0.196% of the 256 TiB virtual space).

Operating mode explanation

The architecture has two primary modes of operation:

Long mode

The architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit, 32-bit and 16-bit (or 80286) protected mode applications may be supported.

Since the basic instruction set is the same, there is no major performance penalty for executing x86 code. This is unlike Intel's IA-64, where differences in the underlying ISA means that running 32-bit code is like using an entirely different processor. However, on AMD64, 32-bit x86 applications may still benefit from a 64-bit recompile, due to the additional registers in 64-bit code, which a high-level compiler can use for optimization.

Legacy mode

The mode used by 16-bit (protected mode or real mode) and 32-bit operating systems. In this mode, the processor acts just like an x86 processor, and only 16-bit or 32-bit code can be executed. 64-bit programs will not run

INTEL 64

Intel 64 is Intel's implementation of x86-64. It is used in newer versions of Pentium 4, Pentium D, Pentium Extreme Edition, Celeron D, Xeon, and Pentium Dual-Core processors, and in all versions of the Core 2 processors.

History of Intel 64

Historically, AMD has developed and produced processors patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting the architecture which AMD had created as an extension to Intel's own x86 processor line.

Intel's project was originally codenamed Yamhill (after the Yamhill River in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett, admitted that this was one of their worst kept secrets.^[4][5]

Intel's name for this technology has changed several times. The name used at the IDF was CT (presumably for Clackamas Technology, another codename from an Oregon river); within weeks they began referring to it as IA-32e (for IA-32 extensions) and in March 2004 unveiled the "official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using the name Intel 64 for its implementation, paralleling AMD's use of the name AMD64.^[6]

Implementations

Intel 64 was originally implemented on the E revision (Prescott) of Pentium 4 line of microprocessors, which were supported by i915P (Grantsdale) and i925X (Alderwood) chipsets in June 2004. This was largely due to the competitive pressure of AMD's AMD64 technology implemented on Opteron and Athlon 64 lines of microprocessing units, otherwise known as the K8 core, one year earlier in 2003; the technology was largely built compatible to AMD64, and the then announced Windows XP Professional x64 Edition supporting AMD64 technology. Intel's first processor to activate the Intel 64 technology was the multi-socket processor Xeon code-named Nocona. Since the Nocona Xeon itself is directly based on Intel's desktop processor, the Pentium 4, the Pentium 4 also has Intel 64 technology built in, although as with Hyper-Threading, this feature was not initially enabled on the then-new Prescott design, likely because enabling Intel 64 did not coincide with Intel's stance on 64-bit x86 extensions at that particular time. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the market as the Pentium 4, model F. However, the revision F core was targeted at workstations. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 Stepping Prescott-2M. The E0 revision also adds eXecute Disable(XD) (Intel's name for the NX bit) support to Intel 64, and has been included in the current Xeon code-named Irwindale. All 9xx, 8xx, 6xx, 5x6, 5x1, 3x6, and 3x1 series CPUs have Intel 64 enabled, as do the Core 2 CPUs, and as will all future Intel CPUs. Intel 64 is also present in the last members of the Celeron D line.

The first Intel mobile processor supporting Intel 64 is the Merom version of the Core 2 processor, which was released on 27 July 2006. None of Intel's earlier notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile Pentium 4) support Intel 64.

The following processors implement the Intel 64 architecture:

• Intel NetBurst
  • Intel Xeon (some models since "Nocona")
  • Intel Celeron D (some models since "Prescott")
  • Intel Pentium 4 (some models since "Prescott")
  • Intel Pentium D
  • Intel Pentium Extreme Edition
• Intel Core microarchitecture
  • Intel Xeon (all models since "Woodcrest")
  • Intel Core 2 (Including Mobile processors since "Merom")
  • Intel Pentium Dual Core (E2140 and E2160)
  • Intel Celeron (Celeron 4x0; Celeron M 5xx)

Differences between AMD64 and Intel 64

There is a small number of differences between the two instruction sets. Compilers generally produce binaries that are compatible with both (that is, compatible with the subset of X86-64 that is common to both AMD64 and Intel 64), making the differences mainly of interest to compiler developers and to operating system developers.

Recent implementations

• Intel 64's BSF and BSR instructions act differently when the source is 0 and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.
• Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).
• Intel 64 lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.
• AMD64 require a different microcode update format and control MSRs while Intel 64 supports microcode update as in 32-bit mode.
• AMD64 lacks the MONITOR and MWAIT instructions, used by operating systems to better deal with Intel's Hyper-threading feature and also to enter specific low power states.
• AMD64 systems allow the use of the AGP aperture as an IOMMU. Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GiB. Intel 64 systems require the use of bounce buffers, which are slower.
• Intel 64 only supports SYSCALL and SYSRET in IA-32e mode (not in compatibility mode). SYSENTER and SYSEXIT are supported in both modes.
• AMD64 lacks support for SYSENTER and SYSEXIT in both sub-modes of long mode.
• Near branches with the 66H (operand size) prefix behave differently. Intel 64 clears only the top 32 bits, while AMD64 clears the top 48 bits.
• AMD64 added support for 1GB pages, in the page table system.

Older implementations

• Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.
• Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are load and store instructions, respectively, for certain status flags. These instructions are used for virtualization and floating-point condition handling.
• Early Intel CPUs with Intel 64 also lack the NX bit (No Execute bit) of the AMD64 architecture. The NX bit marks memory pages as non-executable, allowing protection against many types of malicious code.
• Original AMD64 implementations allowed access only to 2⁴⁰ bytes of physical memory, however, recent AMD64 implementations now provide 2⁴⁸ bytes of physical memory access (with planned expansion to 2⁵² bytes).
• Original Intel 64 implementations allowed access only to 2³⁶ bytes of physical memory, however, recent Intel 64 implementations now provide 2⁴⁰ bytes of physical memory access.

Market analysis

AMD's AMD64 design represents a break with the company's past behavior of following Intel's standards, but emulates Intel's earlier behavior of extending the x86 architecture, from the 16-bit 8086 to the 32-bit 80386 and beyond, without ever removing backward compatibility.

It was long believed that 64-bit RISC chips such as the DEC Alpha would eventually replace the outdated and quirky x86 architecture (which is a direct descendant from 8-bit processors, such as the 8085 and the Z80). Part of the reason this did not happen was the vast investment in software for x86-based systems. Intel, Cyrix, AMD, and others, also quickly found ways to apply modern design principles (inspired by RISC designs, as well as other ideas) transparently, i.e. without changing the basic programming model. A large company, such as Intel, can also employ the latest low-level implementation techniques, which enhances performance regardless of architecture. Furthermore, the 8-bit heritage of the x86 processor line actually helps making good use of limited cache memories, thanks to an inherent small code footprint.

Part of the reason is also that the worst performance problems of the original 8086 and 8087 chips, such as the slow bus-interface, were quickly fixed by the advent of the 80186 and 80286. The 80286 also introduced protected mode, allowing a fully protected operating system to be developed for it (though the protection was segment-based), and increased the physical address space to 24 bits. Registers were still 16 bits however, meaning that the same segment size limitations as in 8088 still applied, though the segmentation was changed to support a larger segmented address space (up to 8192 segments globally and per task, each up to 65536 bytes in size) and also protection. The 80386 (in 1985) then extended the registers to 32 bits, and extended the size of the linear address space, accessible without use of the segmentation architecture, to 2³² bytes. The 80386 also added paging scheme on the bottom of the (now "optional") segmentation. The remaining performance hampering quirks of the original design, such as the stacked x87 registers, has been both largely factored out (by register renaming and other techniques) and, lately, successively replaced, without losing backward compatibility. The x86-64 architecture finally migrates the x86 architecture into a fully 64-bit environment, while maintaining compatibility with legacy software.

As of 2007, a few consumer and business applications are available as 64-bit compiled programs. Video, photo and audio production programs benefit greatly from the larger address space, as running out of memory is a common problem when working with large videos. On the other hand, applications like web browsers and word processors generally do not need to use more than 2 GiB of address space. Nevertheless, their chips' cost-effectiveness has allowed AMD to capture a larger share of the personal computer market, at Intel's expense, simply because of the performance-to-cost ratio and the expected growth capability should 64-bit applications become common. Intel in the summer of 2006 had announced a substantial reduction in net revenue and major restructuring.

From Wikipedia, the free encyclopedia

(jan 2, 2008)