Course Abstract
MindShare’s “DRAM Technology Architecture” course describes the development of computer memory systemsand coversin-depth today’s most advanced DRAM technology. The course ultimately focuses on ultra-dense, high-speed DDR2/DDR3 technology. Memory cell theory, operation and key chip architecture differences from SDRAM through DDR3 is covered. The PC DIMM organization and raw card definitions will be covered, as well as bus implementations. Initialization of a memory module, including an overview of the SMBus protocol and how to use the address strapping is discussed. System design challenges, ranging from signal routing to error handling, are covered. Using waveform examples, the commands and basic differences between SDRAM, DDR, DDR2 and DDR3 are taught. Alternative memory solutions like Fully-Buffered DIMMs, XDRAM, RL DRAM and GDDR are reviewed.DRAM controller design principles are also discussed.
Course Length: 2 Days
Who Should Attend?
This course is Hardware and Firmware centric. It is suitable for both hardware and software engineers. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of DRAM architecture. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.
Course Contents:
- DRAM Introduction
- A brief history of memory from Ferrite core to DDR
- SRAM VS DRAM
- SRAM Example
- DRAM Chip Overview
- Cell architecture
- Internal refresh engine
- Internal architecture examples for SDRAM, DDR1 and DDR2
- 1-2-4 N prefetch
- Internal clock domains
- Sense amp: What is it and how does it relate to the ROW and PAGE
- Pad VS core logic example (split address scheme)
- Package Descriptions and ball spatial locality
- Pin Descriptions
- External clock domains Common clock and source synch examples
- Module Overview
- Added components SPD/registers
- Unbuffered
- Registered
- Raw card definitions
- Module initialization
- SM Bus Overview
- Common clock signal routing
- Differential routing
- Source synchronous routing
- Error modes Hard errors vs. Soft errors; ECC; Address/Command Parity
- SDRAM Overview
- What changed
- Synchronous with clock
- Multiple Banks
- Programmable burst latency
- CKE
- DDR1 Overview
- What changed from SDRAM
- Dual edge Date Rate (2N prefetch)
- DLL was added
- Burst orientation
- Wave forms and command definition (In depth including timings)
- Power management options
- Fast CKE power down
- Suspend to RAM
- DDR2
- What has changed from DDR1
- SSTL1.8 defined
- Burst mode of 4 and 8 only (4 N prefetch)
- ODT including timings
- OCD (not used)
- Posted CAS AKA additive latency
- And command definitions
- DDR3
- Fly-By Routing Read Example
- Read Calibration
- Fly-By Routing Write Example
- Write Leveling
- On-Die Termination
- ZQ Calibration
- Reset
- Package Mirroring
- Mode Register Changes
- System Design Challenges
- Board layout topics
- System architecture topics
- DRAM Controller implementation
- Block diagram
- Description of each functional unit
- Path to FSB and path to IO
- Buffering/Combining unit (read and write paths)
- Refresh Timing control
- Analog calibration unit
- IO Pad control unit
- Physical address conversion
- Control registers
- Overview other types of memory
- RL DRAM
- GDDR
- RAMBUSDRAMs
- FBDRAM
Recommended Prerequisites:
A basic understanding of memory architecture
Booking Information:
This course is available as an in house course and can be tailored to your company's specific needs. For available dates, pricing information or to make a reservation, please contact us.