Course Abstract:
MindShare’s “Intel PC and Chipset Architectures” course provides a detailed and comprehensive understanding of PC system boards designed around Intel chipsets.
The course starts with a broad description of chipset architecture concepts and describes PC design concepts using a generic chipset. The course describes the system’s memory and IO address space. Address decoding in both the Memory Controller Hub (MCH) and IO Controller Hub (ICH) is described. The course then describes the device communication model between processor(s), system memory, boot ROM, peripheral devices and the graphics controller. The course introduces the buses and their related interfaces/pins that connect the system devices to the chipset. This include: the processor bus, DRAM memory bus, PCI Express bus, PCI bus, USB bus, LPC bus, and SATA. The course describes examples of desktop, notebook, workstation and server chipsets. Chipset embedded peripherals such as interrupt and DMA controllers, counter/timers, and the real-time clock (RTC) are described. The course does not describe the internal chipset design details as this information is Intel proprietary, but instead focus on architectural concepts and the operation of chipset related interfaces and relationships between these interfaces.
The course provides in-depth information, example implementations, and practical guidance that will give you a running start on your design or validation.
Course Length: 4 Days
Who Should Attend?
This course is both hardware- and software-oriented. It is suitable for both hardware and software engineers. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of chipset architecture. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers. Firmware and driver software engineers will benefit from understanding how to access the configuration space.
Course Contents:
- Role of the chipset in the system
- Evolution of chipset architecture
- Current chipset architecture overview
- System memory/IO address spaces and chipset address decoding
- Communication model between various devices through the chipset including snoopingprotocol on the processor bus including multi-processor/multi-core MESIcache protocol
- Interfaces related to Memory Controller Hub (MCH)
- Processor bus and interface
- Memory controller and memory bus interface including DDR2 protocol and FBDIMM overview
- PCI Express interface to graphics
- Hub Link and Direct Media Interface (DMI) to ICH
- Clocks, reset and miscellaneous signals
- Interfaces related to IO Controller Hub (ICH)
- PCI Express interface
- PCI/PCI-X interface
- USB interface
- IDE/SATA interface
- Low Pin Count (LPC) interface
- Firmware Hub (FWH) boot ROM interface
- SMBus interface
- AC ‘97 Audio interface
- Ethernet interface
- Interrupt interface and interrupt controllers (8259 and IO APIC)
- DMA controller
- Counter/timer
- RTC and CMOS block
- Power management interface
- Signals that interface to the processor
- Clocks and Miscellaneous Signals
- Configuration register space access mechanism
- MCH register map overview
- ICH registers map overview
- Description of P965, 955X, 925X, 945P/945G and 915G desktop chipsets
- Description of GM965, 915PM, 915GM and 910GMLnotebook chipset
- Description of E7525, E7505, 875P workstation chipsets
- Description of 5000, E8500, E7520 and E7210 server chipsets
Recommended Prerequisites:
A basic understanding of digital design and computer architecture concepts is required.
Booking Information:
This course is available as an in house course and can be tailored to your company's specific needs. For available dates, pricing information or to make a reservation, please contact us.