On-Chip Debugging of ARM, Cortex, PowerPC, XC166, XC2000, XE166, TriCore, Power Architecture, SH-2A

Unrivalled Flexible Target System Access

• JTAG OCDS L1, EmbeddedICE, DAP, SWD are fully supported by UDE offering direct high-speed access to the MCUs internal units.
• OCDS L2, MCDS, ETM and Nexus trace supported.
• ETB trace as internal buffer of trace data is supported by UDE.
• Target ROM monitor and bootstrap loader/RAM monitor solutions for a flexible access via a wide variety of debug channels (ASC, SSC, 3-Pin, CAN) are available (not required to access C166CBC, XC16x, XC22x, TriCore and ARM targets).

Debugging and Emulation via JTAG - Support of OCDS L1, L2, EmbeddedICE, ETM, ETB, DAP, SWD, Nexus
 

JTAG, DAP, SWD, Nexus offer direct access to microcontrollers with an On-Chip Debug and Emulator Support module (e.g. XC2000, TriCore, PowerPC, ARM7, ARM9, ARM11 and XScale). It provides a direct serial interface to the controller-internal functional units (registers, busses, control unit etc.). This way, debugging is performed without monitor software or emulators. The EmbeddedICE is the JTAG-based debugging environment for ARM MCUs. The OCDS L1 and EmbeddedICE are the base of the latest generation of development environments with new features:

• Event Triggering by the on-chip trigger unit, by software breakpoints or by the Break Input pin
• additional execution of data transfers
• complex trigger conditions
• symbolic conditions for enhanced definitions
• task-specific breakpoints automatic selection and optimized usage of the on-chip resources
• access to the entire address space of the controller without any external hard- or software resources
• hardware breakpoints for debugging in ROM or on-chip FLASH
• optimized support for single-chip applications.

Trademarks: ARM, EmbeddedICE, Thumb and Embedded Trace macrocell are trademarks of ARM Limited. TriCore is a trademark of Infineon Technologies.